Testing fabricated integrated circuits to determine proper operation has always been a challenging task, particularly with regard to on-board memory functions.
There are two major types of device malfunctions caused by design defects. A design defect arises when the integrated circuit was manufactured to a design specification that did not provide proper function for the intended use purpose. Such a defect affects any manufactured integrated circuit until the design defect is corrected. The integrated circuit manufacturer must detect and correct such defects before shipping large number of devices to customers to avoid a costly recall. In contrast to a design defect, a manufacturing defect involves some fault in the manufacture of the integrated circuit. A manufacturing defect will generally affect less than all parts manufactured. Such defects are corrected by identification and correction of the manufacturing fault.
Most integrated circuit manufacturers test integrated circuits for proper operation before shipment to customers. Increasing integrated circuit complexity makes this testing increasingly difficult. Rather than rely on increasingly expensive external testing devices, many manufacturers test integrated circuits using a built-in self-test (BIST). BIST uses circuits on the integrated circuit designed solely to test the integrated circuit. When triggered either automatically in circuit operation or by an external test device, the BIST circuits produce a set of test conditions run on the ordinary circuit hardware. Comparison of the state of the integrated circuit following test to an expected state indicates whether the integrated circuit passed. An example of such a test is writing to a read/write memory and recalling the data written. A match between the data written and the data read passes the test. BIST typically involves other more complex tests.
A subset of BIST is programmable built-in self test (pBIST) that uses a general purpose test engine programmed by a set of instructions. This set of test instructions is typically stored on the integrated circuit in a read only memory (ROM) and includes instructions particularly developed for that integrated circuit. pBIST enables re-use of hardware and test instructions to cover a family of similar but not identical integrated circuits.
U.S. Pat. No. 7,324,392 entitled ROM-Based Memory Testing includes a description of an exemplary set of instructions for use in a pBIST. This patent is incorporated by reference in its entirety.
In conventional VLSI systems memory testing is done in three steps. In the first step hardwired logic (often available through third-party vendors, examples are memBIST (MBIST) use algorithms developed before the device is committed to tape-out. Determining the detailed make-up of hardwired logic is not feasible at this time. It is impossible to predict the appropriate hardware circuits because the necessary information comes from process model drivers during the process qualification window. Secondly, conventional memory testing attempts to close testing gaps using CPU based techniques. These techniques have a number of limitations. A major limitation is the CPU interface with largely inaccessible memory functions. The inability to do back-to-back accesses to all memories is another severe limitation. Thirdly, during memory testing while the device is in wafer form direct memory access (DMA) external memory accesses cannot be accomplished at full processor speed. This may result in a significant number of failures not being observable.